Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis)

• ◆Develop and qualify wafer back-grinding, thinning, stress-relief, and backside finishing processes; set thickness, TTV, bow, warp, and roughness targets while minimizing chipping, cracking, subsurface damage, and edge defects
• ◆Develop and optimize mechanical wafer dicing (including thin wafers and difficult materials such as SiC); select blades, tapes, and parameters (speed, feed, depth, coolant, dressing, single- or multi-pass) and control chipping, sidewall quality, delamination, and street/exclusion

• ✓Establish post-dice die cleaning, drying, handling, tape mount/release (UV and non-UV), pick, sort, and presentation methods that protect die integrity, orientation, and traceability for flip-chip, wire-bond, and other assembly flows
• ✓Develop and qualify laser marking processes for wafers and bare die (including green/UV sources); optimize mark contrast and resolution while avoiding damage to electrical performance, metallization, passivation, or mechanical integrity, and implement vision/OCR verification
• ✓Develop final package singulation (saw, laser, or mechanical) for organic, mold, ceramic, and metal structures; minimize cracking, chipping, delamination, burrs, and edge defects and confirm impact on warpage, electrical performance, and reliability
• ✓Run DOEs, define process windows and controls, troubleshoot defects, qualify equipment and consumables, incorporate supplier and production feedback, and transfer robust processes into manufacturing

• ✓Bachelor's degree in chemical engineering, materials science, mechanical engineering, or other engineering discipline
• ✓2+ years of hands-on experience in semiconductor wafer processing, thinning, dicing, die preparation, or manufacturing (Internship or extracurricular experience is applicable)

• ✓3+ years of hands-on semiconductor manufacturing experience, including wafer back-grinding/thinning (including ≤150 µm wafers) and mechanical dicing/blade selection
• ✓Experienced in operating and developing processes on semiconductor equipment, plus solid understanding of wafer and die handling, process troubleshooting, and statistical process control
• ✓Experience with SiC or other hard materials, dicing tapes, blade dressing, two-step or partial-depth cutting, thin-film wafers, and die pick/handling equipment
• ✓Laser marking of wafers or die (green, UV, or similar) and machine-vision/OCR mark verification.
• ✓Package singulation and understanding of warpage, stress, cracking, chipping, and delamination mechanisms
• ✓DOE, SPC, Cp/Cpk, FMEA, or Six Sigma; data analysis with JMP, Minitab, MATLAB, or Python.
• ✓Equipment qualification, process transfer, OSAT/external partner support, and familiarity with JEDEC, SEMI, or IPC standards
• ✓CAD familiarity (AutoCAD or SolidWorks) is a plus

• ✓Onsite in Bastrop, TX (not remote or hybrid)
• ✓Up to 20% domestic and international travel for supplier and manufacturing support
• ✓Willingness to work extended hours or weekends to support key milestones
• ✓Ability to work in a semiconductor manufacturing environment, follow safety and cleanroom requirements, and perform light physical tasks (including lifting up to 25 lbs and handling wafers, substrates, packages, and tooling)
• ✓Strong written and verbal communication skills with engineering, manufacturing, suppliers, and management

ITAR

• ✓To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here .

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