Distinguished Engineer (DE) or Senior Director, Central Engineering – SoC Design & Modeling Methodologies
Renesas Electronics · San Jose, CA
- Level
- Director+
- Team
- Manufacturing
- Experience asked
- 15+ years
- Industry
- Industrial
- Posted
- Today
The role in 30 seconds
A director-level manufacturing role at Renesas Electronics (industrial) in San Jose, CA. In Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (Ph.D.
- They ask for
- 15+ years
- Tools it names
- Validation (IQ/OQ/PQ), Automation
Read from the posting. The full description is below.
From the plant jobs report · week of October 19, 2026
Manufacturing Engineer roles in California: typical posted base $115k–$169k.
Median of the low and high ends of 126 live postings that list pay, out of 346 manufacturing engineer openings in California, read from manufacturers' own careers sites.
California plant jobs report →Pay by team and state →What moves pay →
How this role compares
Against 345 other live manufacturing postings in California.
- Base pay
- Not listed in this posting
- Experience asked
- More than usual (15+ vs 5+)
Typical $111k–$159k, from 113 postings that list pay.
Similar roles usually ask 5+ years.
Skills these teams ask for most
- Tooling 51%
- New product launch 49%
- Root cause 39%
- ✓ Automation 36%
- CATIA / NX 27%
- Machining 27%
✓ = this posting asks for it too. % = share of similar postings that mention it.
At a glance
Pulled from the posting text. If it's not listed here, the posting didn't say.
How to get in at this plant
Five moves over a week or two. The first one takes ten minutes.
- 1
Pick 2–3 people on the Manufacturing team at Renesas Electronics
Engineers who joined in the last year or two reply the most. Use the team search on this page to find them.
- 2
Send a short, curious note
One real question about their work. No favors yet. Each person gets a different note, written for this role.
- 3
Turn a reply into a short call
Questions worth asking about this team:
- What does a normal week look like on your team?
- Is the work mostly new product launches or sustaining existing lines?
- How much time do you spend on the floor versus at a desk?
- How did you land the job? What stood out in your interviews?
- 4
Apply with someone vouching for you
If the call went well, ask whether they’d pass your résumé to the hiring manager. Send your résumé link, apply that day, and let them know.
- 5
Bring proof to the interview
One page of before-and-after numbers from projects you led: scrap, OEE, cycle time, cost. Plant managers hire on results.
Full description from Renesas ElectronicsAs posted on their careers site.ShowHide
requirements
into system-level
requirements
is highly desirable.
The role encompasses workload characterization, solution integration, performance and power tradeoffs, the development of advanced SoC architecture, modeling methodologies, and design enablement strategies across multiple product lines.
The ideal candidate is a recognized technical leader with deep expertise in workload and performance analysis, AI workloads, HW/SW co-design, and SoC architecture. You will partner with product groups, platform teams, and executive leadership to define and analyze products and SoCs for performance and workload analysis, and help co-optimize using next-generation design methodologies that accelerate innovation and enable reuse across the organization.
Education
- ✓MS or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (Ph.D. highly desired).
Experience
- ✓15+ years of experience in semiconductor or SoC development.
- ✓8+ years of technical leadership experience.
- ✓Proven experience leading performance and workload analysis and HW/SW co-optimization.
Show full description ↓Show less ↑
This position will serve as the leader of workload and performance analysis, hardware/software (HW/SW) optimization and co-design (including AI workloads), and SoC architecture. Expertise in architecture, design, validation, HW/SW optimization, and co-design is required. Experience in platform design and translating customer-facing
Technical Leadership
- •Define and drive the strategic roadmap for workload analysis and performance for both IPs and products across the company.
- •Lead architecture performance reviews and technical direction for complex IP/SoC and subsystem developments.
- •Establish best practices for hardware/software co-design and model-based development.
- •Provide technical leadership for cross-functional teams spanning architecture, design, verification, emulation, and software.
AI-Driven Engineering Innovation
- •Define and analyze AI workloads and the performance required for these workloads.
Organizational Leadership
- •Build and lead high-performing engineering teams.
- •Mentor directors, principal engineers, and distinguished engineers.
- •Foster collaboration across Central Engineering, Product Groups, and external partners.
- •Influence long-term semiconductor technology and platform strategy.
Technical Skills
- •Strong understanding of:
- •Performance analysis
- •Workload analysis
- •AI workloads
- •SoC architecture and integration
- •Digital design methodologies
- •IP and subsystem development
- •Hardware/software co-design
- •SoC verification methodologies
- •Hands-on experience with:
- •Performance and workload benchmarking
- •Virtual platforms and executable specifications
- •SoC performance modeling
- •Design and verification automation flows