Senior Analog Engineering Manager
Renesas Electronics · Johns Creek, GA
- Level
- Manager
- Team
- Manufacturing
- Degree
- Preferred
- Experience asked
- 12+ years
- Industry
- Industrial
- Posted
- 3 days ago
The role in 30 seconds
A management manufacturing role at Renesas Electronics (industrial) in Johns Creek, GA.
- They ask for
- 12+ years · degree preferred
- Tools it names
- Validation (IQ/OQ/PQ)
Read from the posting. The full description is below.
From the plant jobs report · week of October 19, 2026
Manufacturing Engineer roles in Georgia: typical posted base $95k–$123k.
Median of the low and high ends of 5 live postings that list pay, out of 17 manufacturing engineer openings in Georgia, read from manufacturers' own careers sites.
Georgia plant jobs report →Pay by team and state →What moves pay →
How this role compares
Against 16 other live manufacturing postings in Georgia.
- Base pay
- Not listed in this posting
- Experience asked
- More than usual (12+ vs 5+)
Typical $95k–$123k, from 5 postings that list pay.
Similar roles usually ask 5+ years.
Skills these teams ask for most
- Tooling 65%
- Root cause 47%
- New product launch 41%
- Lean 41%
- ✓ Validation (IQ/OQ/PQ) 29%
- Machining 29%
✓ = this posting asks for it too. % = share of similar postings that mention it.
At a glance
Pulled from the posting text. If it's not listed here, the posting didn't say.
How to get in at this plant
Five moves over a week or two. The first one takes ten minutes.
- 1
Pick 2–3 people on the Manufacturing team at Renesas Electronics
Engineers who joined in the last year or two reply the most. Use the team search on this page to find them.
- 2
Send a short, curious note
One real question about their work. No favors yet. Each person gets a different note, written for this role.
- 3
Turn a reply into a short call
Questions worth asking about this team:
- What does a normal week look like on your team?
- Is the work mostly new product launches or sustaining existing lines?
- How much time do you spend on the floor versus at a desk?
- How did you land the job? What stood out in your interviews?
- 4
Apply with someone vouching for you
If the call went well, ask whether they’d pass your résumé to the hiring manager. Send your résumé link, apply that day, and let them know.
- 5
Bring proof to the interview
One page of before-and-after numbers from projects you led: scrap, OEE, cycle time, cost. Plant managers hire on results.
Full description from Renesas ElectronicsAs posted on their careers site.ShowHide
Preferred Qualifications
- ✓Direct involvement in DDR6 architectural studies or early-stage development.
- ✓Experience at advanced nodes (7nm, 5nm, and below).
- ✓Background in multi-generation memory PHYs or scalable PHY platforms.
- ✓Ability to lead teams delivering multiple concurrent tape-outs.
- ✓Strong written and verbal communication skills across technical and executive audiences.
Show full description ↓Show less ↑
Technical Leadership (DDR5 / DDR6)
- •Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.
- •Provide technical oversight for critical analog and mixed-signal blocks, including:
- •High-speed TX/RX datapaths
- •Advanced equalization, termination, and training circuits
- •DLL/PLL-based clocking solutions for multi-GHz operation
- •Voltage, reference generation, and power-aware IO design
- •Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates.
- •Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction.
- •Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation.
People & Organization Leadership
- •Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces.
- •Set technical direction, performance expectations, and development plans for senior and principal engineers.
- •Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs.
- •Foster a culture of technical rigor, ownership, and execution excellence.
Program & Cross-Functional Execution
- •Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk
- •Partner closely with: Digital PHY and controller teams SoC integration and system architecture, Package, PCB, SI/PI, and validation teams, Product, program management, and customers
- •Interface with foundries, IP vendors, and standards bodies as needed to ensure successful delivery and future readiness.
Methodology, Quality & Roadmap
- •Establish robust design and signoff methodologies for next-generation high-speed PHYs.
- •Drive continuous improvement in simulation accuracy, mixed-signal verification, and silicon debug efficiency.
- •Lead long-term DDR5 sustainment and DDR6 technology roadmap planning, including architectural trade-offs and scaling strategies.
- •Anticipate challenges from data-rate scaling, power efficiency, and advanced process technologies
- •Bachelor’s or Master’s degree in Electrical Engineering (PhD preferred).
- •12+ years of experience in analog/mixed-signal IC design with deep focus on high-speed memory interfaces.
- •5+ years of people-management and technical leadership experience.
- •Proven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5
- •Strong expertise in: High-speed IO design and signal integrity, PLL/DLL and low-jitter clocking architectures,Mixed-signal verification and silicon validation, Advanced CMOS process considerations for IOs
Leadership Profile
- •High technical credibility with the ability to dive deep when needed
- •Strong execution mindset with disciplined risk management
- •Effective mentor and team builder
- •Strategic thinker with a roadmap-driven approach to DDR evolution
- •Comfortable balancing hands-on engagement with organizational leadership