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Principal Design Automation Engineer

Micron · San Jose, CA

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Level
Senior
Team
Controls
Base pay
$176k–$298k
Experience asked
8+ years
Industry
Industrial
Posted
30+ days ago

The role in 30 seconds

A senior controls role at Micron (industrial) in San Jose, CA. Inc., you will drive the transformation of NAND circuit development through design automation, agentic circuit-design enablement, and environment transition!

They ask for
8+ years
Tools it names
Validation (IQ/OQ/PQ), Automation, Tooling
Base pay
$176k–$298k
Day to day
some off-shift / weekend coverage

Read from the posting. The full description is below.

How this role compares

Against 82 other live controls postings in California.

Base pay
About 57% above similar roles

Typical $123k–$179k, from 54 postings that list pay.

Experience asked
More than usual (8+ vs 5+)

Similar roles usually ask 5+ years.

Skills these teams ask for most

  • ✓ Automation 60%
  • PLC 45%
  • ✓ Python 40%
  • ✓ Validation (IQ/OQ/PQ) 37%
  • Robotics 31%

✓ = this posting asks for it too. % = share of similar postings that mention it.

It asks for 8+ years. If you're close, apply anyway: requirements are a wish list. Talk to someone on the team first.

At a glance

Off-shift / weekend coverage

Pulled from the posting text. If it's not listed here, the posting didn't say.

How to get in at this plant

Five moves over a week or two. The first one takes ten minutes.

  1. 1

    Pick 2–3 people on the Controls team at Micron

    Engineers who joined in the last year or two reply the most. Use the team search on this page to find them.

  2. 2

    Send a short, curious note

    One real question about their work. No favors yet. Each person gets a different note, written for this role.

  3. 3

    Turn a reply into a short call

    Questions worth asking about this team:

    • What does a normal week look like on your team?
    • How does off-shift and weekend coverage work?
    • How did you land the job? What stood out in your interviews?
  4. 4

    Apply with someone vouching for you

    If the call went well, ask whether they’d pass your résumé to the hiring manager. Send your résumé link, apply that day, and let them know.

  5. 5

    Bring proof to the interview

    One page of before-and-after numbers from projects you led: scrap, OEE, cycle time, cost. Plant managers hire on results.

Full description from MicronAs posted on their careers site.Show

Qualifications

  • ✓MS (PhD preferred) in electrical engineering required. 8+ years of NAND design relevant proven experience required with proficient knowledge of Nand Flash memory read, program and erase algorithms
  • ✓Proficiency in analog/mixed signal circuit design (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog)
  • ✓Proficiency in analog/mixed signal circuit layout (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog)
  • ✓Proficient fundamentals in semiconductor and device physics and analog/mixed-signal circuit design. An understanding of semiconductor reliability issues including CHC, NBTI, stress, and snapback, as well as Electromigration (EM) and IR analysis.
  • ✓Proficiency in circuit verification and optimization, layout planning, parasitic extractions of the circuits, experience guiding layout. Strong understanding of circuit design verification flows, including block‑level, subsystem‑level, and full‑chip simulations, corner management, PVT/mismatch analysis, and results qualification. analog and digital simulators such as HSPICE, Fast SPICE, and Verilog
  • ✓Proven proficiency in Python for engineering automation, including development of maintainable scripts, libraries, or frameworks that collaborate with EDA tools for simulation control, data extraction, regression management, or reporting. Proficient with Cadence design, LVS/DRC tools and UNIX

$176,000.00 - $298,000.00 a year

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .

Show full description ↓

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Staff/Principal Design Engineer in the NVE Design Engineering organization at Micron Technology, Inc., you will drive the transformation of NAND circuit development through design automation, agentic circuit-design enablement, and environment transition!

  • •Implementing core Xpath, Ypath and Array design during project execution and work with project teams integrating the Core schematics into the full chip schematics, validating design performance and functionalities by running block and chip level simulations using standard industry simulators!
  • •Implementing analog and mixed signal circuit design (charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, LDO, thermometers, page buffers, PDNs, level shifters, IO buffers, RTL, Verilog) to meet specifications, validating design performance and functionalities by running block and chip level simulations using standard industry simulators
  • •Serve as a technical authority across analog/core teams , solving sophisticated technical problems at the intersection of circuit behavior, modeling, simulation methodology, and automation reliability
  • •Develop and productize agentic enablement for circuit design , including AI/LLM-assisted flows that support:
  • •environment setup and self-healing configuration,
  • •guided simulation and debug,
  • •intelligent corner planning and coverage closure,
  • •automated schematic/layout checks and review assistance,
  • •documentation synthesis and knowledge retrieval from internal sources,
  • •block/subsystem/full-chip verification (analog/mixed-signal), including reproducible run recipes, golden reference management, and regression gating criteria
  • •Integrate automation with project execution , partnering with circuit designers, firmware, validation, and architecture teams to align tooling with breakthrough needs and deliver measurable cycle-time reduction.
  • •Collaborate with multi-functional team members** (Product Engineering, Test, Probe, Process Integration, Assembly, Marketing) to ensure automation and environment choices support manufacturability, testability, reliability, time-to-market, and customer happiness.

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