Sr Director, XSE Design Verification Engineering Manager
Intel · California
- Level
- Director+
- Team
- Manufacturing
- Base pay
- $256k–$361k
- Degree
- Required
- Experience asked
- 12+ years
- Industry
- Industrial
- Posted
- Today
The role in 30 seconds
A director-level manufacturing role at Intel (industrial) in California. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
- They ask for
- 12+ years · degree required
- Tools it names
- Validation (IQ/OQ/PQ)
- Base pay
- $256k–$361k
Read from the posting. The full description is below.
From the plant jobs report · week of October 26, 2026
Manufacturing Engineer roles in California: typical posted base $112k–$168k. This one lists $256k–$361k.
Median of the low and high ends of 136 live postings that list pay, out of 363 manufacturing engineer openings in California, read from manufacturers' own careers sites.
California plant jobs report →Pay by team and state →What moves pay →
How this role compares
Against 362 other live manufacturing postings in California.
- Base pay
- About 130% above similar roles
- Experience asked
- More than usual (12+ vs 5+)
Typical $110k–$159k, from 120 postings that list pay.
Similar roles usually ask 5+ years.
Skills these teams ask for most
- Tooling 52%
- New product launch 50%
- Root cause 39%
- Automation 36%
- CATIA / NX 28%
- Machining 27%
✓ = this posting asks for it too. % = share of similar postings that mention it.
At a glance
Pulled from the posting text. If it's not listed here, the posting didn't say.
How to get in at this plant
Five moves over a week or two. The first one takes ten minutes.
- 1
Pick 2–3 people on the Manufacturing team at Intel
We found 6 people at this company and state: 5 in this kind of role, 1 leaders. Engineers who joined in the last year or two reply the most. See them ↓
- 2
Send a short, curious note
One real question about their work. No favors yet. Each person gets a different note, written for this role.
Write to Matt → (free) - 3
Turn a reply into a short call
Questions worth asking about this team:
- What does a normal week look like on your team?
- Is the work mostly new product launches or sustaining existing lines?
- How much time do you spend on the floor versus at a desk?
- How did you land the job? What stood out in your interviews?
- 4
Apply with someone vouching for you
If the call went well, ask whether they’d pass your résumé to the hiring manager. Send your résumé link, apply that day, and let them know.
- 5
Bring proof to the interview
One page of before-and-after numbers from projects you led: scrap, OEE, cycle time, cost. Plant managers hire on results.
Full description from IntelAs posted on their careers site.ShowHide
The Role and Impact
As a Design Verification Engineering Manager, you will lead a dynamic team of design verification engineers responsible for Xeon SoC design verification. You will deploys and manage leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. You will work with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. You will also bring a culture of rapid execution with high quality and simplify complicated process flows. This critical role ensures delivery excellence, directly contributing to Intel's broader success in creating innovative technology solutions.
Business group
The Data Center Group (DCG) is at the forefront of Intel's mission to deliver advanced technologies that power cloud computing, enterprise, AI, and edge solutions. Within DCG, the DSE Xeon SoC Engineering organization specializes in developing cutting-edge SoC designs to drive next-generation data center performance. Joining this team means being part of a collaborative environment dedicated to shaping the future of data-driven innovation.
Key Responsibilities
- ◆Present status of Verification and quality of design to senior executives in clear and concise manner and present solutions when design hits critical issues.
- ◆Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validation, hackathon reviews, and new validation techniques to improve security coverage. Executes security and security development lifecycle tasks per job role and schedule milestones.
- ◆Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
- ◆Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Create future technical leaders who imbibe the rapid execution and can-do attitude.
Qualifications
- ✓Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, or a related field.
- ✓12+ years of experience in ASIC/SoC design and verification with a Bachelor's degree, 8+ years with a Master's degree, or 6+ years with a PhD.
- ✓Comprehensive knowledge of industry-standard protocols.
Preferred Qualifications
- ✓Proven experience in formal people management or leadership roles, with 5-10+ years in managing technical teams.
- ✓Familiarity with AI and GPU technologies.
- ✓Experience with hardware emulation platforms.
- ✓Strong interpersonal and communication skills to effectively lead cross-functional teams and drive results.
We invite you to bring your leadership, technical expertise, and passion for innovation to Intel, where you'll have the opportunity to make a meaningful impact on groundbreaking technologies.
Show full description ↓Show less ↑
Shift
Shift 1 (United States of America)
Primary Location
US, California, Santa Clara
Posting Statement
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.